Consumer demand for electronic devices capable of high operating speeds continues to provide significant motivation for the development of integrated circuits capable of enhanced device performance. Advanced lithographic and direct writing patterning techniques, for example, currently enable microprocessor designs having large scale integration of 10 s to 100 s of millions of microsized device components in dense multilevel configurations. Critical to practical implementation of such high density device geometries, however, is the development of interconnect structures capable of establishing effective electrical interconnection of functional device components in and between individual device levels of a multilayer electronic device. Commonly, a complex pattern of interconnects and vias in these devices provides a communication mechanism between functional components of the device. The electrical resistance and parasitic capacitance associated with such complex interconnect structures is currently a significant factor in the circuit speeds attainable in modern microprocessor systems. Accordingly, significant research is currently directed toward developing new device geometries, materials and processing strategies for making multilevel interconnects for dense integrated circuits.
Dual Damascene (DD) processing provides an effective means of making complex multilayer metal structures in low-k dielectric materials useful as interconnects in advanced, high performance integrated circuits. In this process, multilevel recessed features comprising interconnected horizontal trenches and vertical via structures are generated in a low-K dielectric layer (e.g., k<3.0)) provided on a substrate using a combination of lithographic pattering and etching techniques. Typically, trenches are etched to a depth of 400 to 500 nanometers and vias are etched to a depth of 500 to 800 nanometers. Trench and via structures are filled in a single metal deposition step followed by chemical mechanical polishing to generate inlaid metal structures capable of establishing intra-level electrical contact between device components occupying a given device level and inter-level electrical contact between device components provided on different device levels. Metal filled trench structures, for example, may provide for wiring of functional device components provided on a given device level, and metal filled via structures may provide contacts for electrically connecting different levels in a device. Copper is a commonly used metal for Dual Damascene interconnect structures, but attention is currently being given to incorporate higher conductivity metals, such as silver, that are less susceptible to diffusion into low k dielectric materials. As a versatile processing platform, Dual Damascene processing is compatible with iterative process implementation on a single device substrate so as to access complex multilayer structures useful for interconnecting a desired number (e.g., eight or more) of individual device levels.
A number of important advantages are provided by the Dual Damascene processing platform. First, this process is compatible with fabrication of low resistance interconnect structures comprising copper as the conducting material. This aspect of Dual Damacene processing is beneficial because alternative plasma etching patterning techniques are generally unavailable and/or unfeasible for patterning copper interconnect structures. Second, use of a single metal deposition step for fabricating trench and via structures provides an accurate means of aligning and registering trench and via structures of an interconnect, thereby minimizing problems arising from device component misalignment. Third, Dual Damascene processing realizes a net reduction in the total number of processing steps required for interconnect formation compared to conventional interconnect fabrication approaches. Defining trench and via structures via Dual Damascene methods requires a single lithographic alignment step and a single deposition step for simultaneously filing both vias and trenches. As a result of these benefits, Dual Damascene processing continues to achieve wide commercial implementation, particularly with respect to Very Large Scale Integrated (VLSI) and Ultra large Scale Integrated (ULSI) devices, such as complementary high performance metal oxide semiconductor (CMOS) devices.
Although current Dual Damascene approaches reduce the total number of processing steps required to make complex multilevel interconnect structures, this fabrication technique still requires a significant number of discrete processing steps (e.g., 20-30) per layer of a multilayer electronic device. A significant component of the processing steps required for Dual Damascene processing currently involves defining trench and via structures in the Dual Damascene profile. There are two primary fabrication schemes for making Dual Damascene profiles in a dielectric layer, (i) the Trench First Dual Damascene process, and (ii) the Via First Dual Damascene process. A Self Aligned Dual Damascene process has also been developed providing an alternative processing route for making Dual Damascene profiles. This process employs a complex fabrication sequence relative to Trench First and Via First processes, however, and is currently not significantly implemented for main stream manufacturing of semiconductor devices.
Trench First and Via First Dual Damascene processing techniques each typically employ a stack of at least three discrete layers of dielectric material comprising a bottom most dielectric layer, etch stop layer and outer most dielectric layer. The bottom most layer is provided on the device substrate. Via structures are etched in this bottom most layer which is typically a silicon dioxide or other low k dielectric material layer having a thickness of 500-700 nm. The etch stop layer, typically consisting of a thin layer of silicon nitride (usually about 30 nm), is provided on top of the bottom most layer. Finally, an outer most dielectric layer is provided on top of the etch stop layer. Trench structures are etched in this outermost dielectric layer, which typically consists a silicon dioxide or other low k dielectric layer having a thickness 400-500 nm.
In the Trench First Dual Damascene fabrication procedure, trenches are first defined in the outermost layer of dielectric material. In an embodiment, for example, a layer of photoresist is first applied on the wafer having the stack of three dielectric layers. A trench pattern is transferred on to the resist using optical lithography. Commonly, a deep UV source or an i-line source is used, depending on the desired trench feature sizes. Once the pattern is exposed, the wafer is immersed in a developer solution, clearing away the exposed regions. The wafer is then anisotropically etched, for example using reactive ion etching (RIE). In this processing step, trench features are etched in the outermost dielectric layer down to the etch stop layer provided between outermost and bottom most dielectric layers of the stack After etching processing is completed, the photoresist is stripped and a second layer of resist is applied on to the dielectric layer stack having the pattern of trench features. The second photoresist layer is patterned corresponding to the via structures after alignment with the trenches etched into the outermost dielectric layer. After development processing, the vias structures are generated via anisotropic etching, for example using reactive ion etching (RIE), wherein the vias extend into the bottom most dielectric layer.
In contrast to the Trench First Dual Damascene fabrication procedure, via structures are patterned before the trench structures in the Via First Dual Damascene fabrication procedure. In this process, the wafer is first coated with a layer of resist and a pattern of a photomask corresponding to the vias is transferred on to the resist using optical lithography. After development of the exposed layer of photoresist, via structures are anisotropically etched completely through the three layer dielectric stack. Once the vias are patterned, a second layer of photoresist is applied to the surface of the dielectric stack having the etched vias structures. The second photoresist layer is patterned using optical lithography to define the trench structures. Upon development of the patterned second photoresist layer, trench structures are etched down to the etch stop layer via anisotropic etching.
Trench First and Via First Dual Damascene techniques are susceptible to a number of disadvantages. First, use of multiple resist processing steps adds considerably to the cost of commercial implementation, as the overall cost of semiconductor device fabrication increases at an exponential rate with the number of resist deposition, patterning developing steps in a given process. Second, Trench First and Via First Dual Damascene require two separate anisotropic etch processing sequences which decreases overall throughput and also significantly increases cost of this fabrication method. Finally, the Trench First Dual Damascene fabrication procedure requires that a second layer of resist be applied onto the wafer after defining and etching the trench structures. Since the resist is commonly in the liquid phase it fills the trench structures etched into the outermost dielectric layer, and therefore, commonly does not form a uniform layer of photoresist if applied too thin. In order to get a uniform coating, the resist layer commonly needs to be very thick, which commonly impedes forming very fine and/or high resolution features of the via structures in the dielectric material.
Given practical limitations of Trench First and Via First techniques employing multiple photoresist processing steps, substantial motivation exists for development of methods for generating Dual Damascene structures using single layer photoresist processing. U.S. Pat. No. 6,355,399 discloses methods using a gray tone mask to form Dual Damascene profiles in a single masking and etch step involving one exposure step. In this method, the intensity of electromagnetic radiation transmitted by a gray scale mask is spatially modified selectively so as to define via and trench structures in a single layer of photoresist. A single resist layer is patterned using the grayscale photomask and, the pattern in the photoresist is subsequently transferred to a dielectric device layer to form via structures corresponding to completely transmissive regions of the photomask and trench structures corresponding to partially transmissive regions of the photomask. U.S. Pat. No. 5,976,968 discloses a method for making Dual Damascene profiles using a phase-shifting photomask in conjunction with a single photoresist process. A phase-shifting photomask is provided having opaque, semi-transmitting and transparent regions that is capable of selectively modulating the spatial distribution of electromagnetic radiation provided to a photoresist layer provided on top of a tri-layer insulating layer. In the disclosed methods, phase-shifting photomask is reported as useful for making Dual Damascene structures in the tri-layer insulating layer. The single photoresist processing strategies described in U.S. Pat. Nos. 6,355,399 and 5,976,968 lack processing flexibility, however, and also require a large photomask library for commercial implementation. For example, specific photomasks in the library are required for each trench and via geometry to be patterned and specific photomasks in the library are required for processing techniques using different resist materials and/or different resist thicknesses.
It will be appreciated from the foregoing that that there is currently a need for Dual Damacene processing methods capable of generating interconnect structures for high performance integrated electronics. Processing methods are needed that are capable of generating complex Dual Damascene profiles comprising networks of integrated trench and via structures. It will also be appreciated that a need exists for Dual Damascene processing methods using a single photoresist process and providing enhanced flexibility relative to conventional single resist Dual Damascene processing techniques.